-- Entity mult128
-- Architecture: VHDL
-- Author: Spencer Shimko (sshimko1)
-- Created: 03/16/04
-- Modified: 03/16/04

library ieee;
use ieee.std_logic_1164.all; 
use ieee.numeric_std.all;

entity mult128 is port(
	clk:		in std_ulogic; -- clocked input
	enable: 	in std_ulogic; -- enable/disable
	multiplier:	in std_ulogic_vector(63 downto 0); -- 64bit multiplier
	multiplicand:	in std_ulogic_vector(63 downto 0); -- 64bit multiplicand,128bit is in signals below
	product:	out std_ulogic_vector(127 downto 0)); -- output product
end mult128;

architecture behavioral of mult128 is
begin
mul: process(clk,enable, multiplier, multiplicand)
  -- the 128bit register for sumation
  variable sum: std_ulogic_vector(127 downto 0) := X"00000000000000000000000000000000";
  -- the 64bit multiplier shift storage vector
  variable multplr: std_ulogic_vector(63 downto 0) := multiplier;
  -- the 128bit multiplicand storage register
  variable multplcnd: std_ulogic_vector(127 downto 0) := multiplicand;
	begin
		-- when we are enabled and hit the rising edge of the clock
		if (rising_edge(clk) and enable = '1') then 
			for i in 0 to 63 loop -- iterate over bits in multiplier
				if (multplr(0) = '1') then -- if its a 1 in the LSB add to sum
					sum := std_ulogic_vector( (unsigned(sum) + unsigned(multplcnd)) );
				end if;
				-- regardless of LSB we shift left the multiplicand
				multplcnd := std_ulogic_vector( unsigned( multplcnd ) sll 1 );
				-- and shift right the multiplier
				multplr := std_ulogic_vector( unsigned( multplr )srl 1 );
			end loop; -- for each bit in mulitplier
		end if; -- if rising clock and enabled
		product<=sum;
	end process mul;
end  behavioral;