-- entity mult64
-- Architecture: VHDL
-- Author: Spencer Shimko (sshimko1)
-- Created: 03/16/04
-- Modified: 03/22/04

--library STD;
--use STD.textio.all;
library ieee;
use ieee.std_logic_1164.all; 
--use IEEE.std_logic_textio.all;
use ieee.numeric_std.all;

entity mult64 is port(
	multiplicand:	in unsigned(63 downto 0); -- 64bit multiplicand,128bit is in signals below
	multiplier:	in unsigned(63 downto 0); -- 64bit multiplier
	product:	out unsigned(127 downto 0)); -- output product
end mult64;

architecture behavioral of mult64 is
begin
mul: process(multiplicand,multiplier)
  -- the 128bit register for vector
  variable sum: unsigned(127 downto 0) := X"00000000000000000000000000000000";
  -- the 64bit multiplier shift storage vector
  variable multplr: unsigned(63 downto 0);
  -- the 128bit multiplicand storage vector
  variable multplcnd: unsigned(127 downto 0);
	begin
		multplr := multiplier;
		multplcnd := resize(unsigned(multiplicand),128);

			for i in 0 to 63 loop -- iterate over bits in multiplier
				if (multplr(0) = '1') then -- if its a 1 in the LSB add to sum
					sum := unsigned( (unsigned(sum) + unsigned(multplcnd)) );
				end if;
				-- regardless of LSB we shift left the multiplicand
				multplcnd := unsigned( unsigned( multplcnd ) sll 1 );
				-- and shift right the multiplier
				multplr := unsigned( unsigned( multplr )srl 1 );
			end loop; -- for each bit in mulitplier
	
		product<=sum;
	end process mul;
end  behavioral;


-- Entity MULTTEST 
-- Architecture: VHDL
-- Author: Spencer Shimko (sshimko1)
-- Created: 03/16/04
-- Modified: 03/22/04

entity MULTTEST is
end MULTTEST;

library STD;
use STD.textio.all;

library IEEE;
use IEEE.std_logic_textio.all;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

architecture test of MULTTEST is
	-- setup file handles
   	file resultFile : TEXT open write_mode is "result.txt";
   	file inputFile : TEXT open read_mode is "ops.txt";
	
	-- setup signals for driver
	signal multiplicand : unsigned (63 downto 0);
	signal multiplier : unsigned (63 downto 0);
	signal product : unsigned (127 downto 0);
   
	-- setup interface to the multiplier
	component mult64
	port ( multiplicand : in unsigned;
               multiplier : in unsigned;
               product : out unsigned
        );
   	end component mult64;

	procedure ReadInputs (
                signal multiplicand : out unsigned;
                signal multiplier : out unsigned) is
                variable fileLine : LINE;
                variable valueRead : std_logic_vector (63 downto 0);
        begin

            readline (inputFile, fileLine);
            read (fileLine, valueRead);
            multiplicand <= unsigned(valueRead);

            readline (inputFile, fileLine);
            read (fileLine, valueRead);
            multiplier <= unsigned(valueRead);

        end ReadInputs;

	procedure DumpOutput (signal product : unsigned) is
                variable fileLine : LINE;
    	begin
        	write (fileLine, std_logic_vector(product));
        	writeline (resultFile, fileLine);
 	end DumpOutput;
begin
--Read the  inputs from the file
   ReadInputs (multiplicand, multiplier);
   mul1:mult64 port map (multiplicand=>multiplicand, 
			multiplier=>multiplier, product=>product);

--Write the output to a file
   writeResult : process
   begin
           wait for 160 ns;
           DumpOutput (product);
           wait;
   end process;

end test;